Instruction decode cluster offlining
US12423103B2 · kind B2 · utility
0Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2021 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Nov 2, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of an integrated circuit may comprise a core and an instruction decoder communicatively coupled to the core to decode one or more instructions for execution by the core, where the instruction decoder includes two or more decode clusters in a parallel arrangement, and circuitry to offline a decode cluster of the two or more decode clusters. Other embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.