Cache governance in a computing environment with multiple processors
US12423234B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2024 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Jul 23, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for cache governance includes receiving, at a local cache of a processor chip, a first fetch request for data for a cache line of the local cache. The method further includes allocating a first cache controller to allow the first fetch request to receive the data and to track reception of the data. The method further includes receiving, at the local cache of the processor chip, a second fetch request for the data for the cache line of the local cache. The method further includes determining via an address compare logic associated with the local cache whether the first fetch request in the first cache controller is for a same cache line that the second fetch request is targeting. The method further includes allowing the second fetch request to allocate a second cache controller and copying metadata from the first cache controller to the second cache controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.