Layout repairing method and apparatus, computer device, and storage medium
US12423497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Apr 23, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a layout repairing method and apparatus, a computer device, and a storage medium. The method includes: obtaining an initial layout of a semiconductor integrated circuit, wherein a metal connection line is formed on the initial layout; forming a power fill grid on the initial layout, wherein the power fill grid includes a slotted hole that overlaps orthographic projection of the metal connection line on the power fill grid, and the slotted hole includes a first section overlapping the metal connection line and at least one second section staggered with the metal connection line; and increasing area of the second section if the area of the second section is less than a lower threshold, to form a repaired layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.