Stacked memory with a timing adjustment function
US12424264B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2023 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Oct 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B80/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked memory with a timing adjustment function is provided, including a logic chip; a memory chip coupled to the logic chip in a face-to-face manner and including plural memory tiles; plural timing adjustment devices, respectively provided in each memory tile, wherein for each memory tile, each timing adjustment device further includes a first timing adjustment device that is configured to adjust setup times and hold times for a command and an address with respect to an edge of a clock signal and a second timing adjustment device that is configured to adjust a setup time and a hold time for input data with respect to the edge of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.