Multiport memory cells including stacked active layers
US12424276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Feb 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multiport memory cell for register files is disclosed. Vertically stacked top and bottom tier of the memory cell are electrically interconnected through a pair of vias and comprise each an active device layer and a metal layer stack. The memory cell is partitioned to have a latching circuit and at least one write port located in the bottom tier and at least two read ports in the top tier. A word line trace for controlling the at least one write port is formed in the bottom tier metal layer stack and comprises two terminal sections and one intermediate section oriented perpendicularly to the terminal sections. The intermediate section is arranged between the pair of vias in a height direction of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.