Compliant pad spacer for three-dimensional integrated circuit package
US12424509B2 · kind B2 · utility
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8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Jan 5, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/2036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A compliant pad spacer utilized in a three-dimensional IC packaging is provided. The compliant pad spacer may be utilized to provide adequate support among the substrates or boards, such as packing substrates, interposers or print circuit broads (PCBs), so as to minimize the effects of substrate warpage or structural collapse in the IC packaging. In one example, the compliant pad spacer includes an insulating material, such as silicon-based polymer composites having ceramic fillers disposed therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.