Patent · US Active

Package with a substrate comprising embedded escape interconnects and surface escape interconnects

US12424559B2 · kind B2 · utility

0Cited by

0References

23Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Kuiwon Kang · San Diego, US
Hong Bok We · San Diego, US
Michelle Yejin Kim · San Diego, US

Key dates

Filing date	Mar 1, 2022
Grant date	Sep 23, 2025
Priority date	—
Expiry date	May 4, 2044

Classification

Technology area (CPC H)Electricity
CPC primaryH05K2201/10734
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer, and a plurality of interconnects comprising a plurality of escape interconnects. The plurality of escape interconnects includes a first embedded escape interconnect, a second embedded escape interconnect, and a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.