Semiconductor structure with a plurality of connection lines
US12426240B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Mar 2, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
Abstract
Embodiments relate to the field of semiconductors, and provide a semiconductor structure, including a substrate and connection lines. Structural cells arranged in an array are provided on the substrate, and include transistor groups arranged in a first direction, and the transistor groups include multi-layer transistors extending in a second direction. The first direction is perpendicular to the second direction, and both are parallel to a surface of the substrate. The structural cells further include bit lines extending in a third direction, the bit lines are electrically connected to the multi-layer transistors in the same transistor group, where the third direction is perpendicular to the surface of the substrate. The connection lines are connected to the bit lines in the structural cells in one-to-one correspondence, and one bit line in the structural cells arranged in the array is connected to the same connection line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.