Semiconductor devices
US12426248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2024 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Jan 23, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device including partially etching an upper portion of a substrate to form a recess extending in a first direction parallel to an upper surface of the substrate, forming a gate structure in the recess, the gate structure including a first conductive pattern, a second conductive pattern on the first conductive pattern, and a gate mask on the second conductive pattern, partially etching an end portion of the gate structure in the first direction to form an opening, the opening extending through end portions of the gate mask and the second conductive pattern of the gate structure to expose a portion of the first conductive pattern, and a bottom of the opening being lower than a lower surface of the exposed portion of the first conductive pattern, and forming a contact plug in the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.