High-voltage semiconductor devices and methods of formation
US12426296B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | May 27, 2022 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Nov 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
Interlayer dielectric (ILD) layer(s) of a semiconductor device may be configured as a gate oxide for high-voltage transistors, and therefore additional process operations to deposit dedicated gate oxide layers are not needed. Moreover, additional processing operations to form the gate structures of the high-voltage fin-based PMOS transistors and high-voltage fin-based NMOS transistors are not needed in that middle end of line (MEOL process and back end of line (BEOL) processes can be used as the gate formation process of the high-voltage transistors.
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