Multistage compiler architecture
US12430108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Jan 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.