Technologies for interconnect address remapper with event recognition and register management
US12430132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Mar 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.