Out-of-order programming of first wordline in a physical unit of a memory device
US12430246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Dec 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array comprising memory cells associated with a plurality of wordlines control logic that is to perform operations including: causing memory cells of a physical unit of the memory array to be programmed starting at a second wordline, which is adjacent to a first wordline of the memory array, and proceeding sequentially through a plurality of sequentially-ordered wordlines of the physical unit, wherein the first wordline is associated with memory cells that are adjacent to one or more select gate (SG) transistors of the memory array, and the sequentially-ordered wordlines are numbered according to a distance away from the one or more SG transistors; and at least one of after the memory cells associated with the second wordline are programmed or after completion of programming the physical unit, causing the memory cells associated with the first wordline to be programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.