Memory system
US12431190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 19, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system for speeding up a read operation in the memory system includes a first pillar, a first string including a first transistor and a first memory cell, a second string including a second transistor and a second memory cell, a first bit line, a first gate line, a first word line, a second gate line, a second word line and a control circuit. When the control circuit executes a read operation with respect to the first memory cell, the control circuit is configured to apply a read voltage to the first word line, apply a voltage turning off the second memory cell regardless of an electric charge stored in the second memory cell to the second word line, apply a voltage turning on the first transistor to the first gate line, and apply a voltage turning on the second transistor to the second gate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.