Memory device and operating method of the memory device
US12431199B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 20, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Dec 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, and an operating method of the memory device, includes a plurality of memory cells connected between word lines and bit lines and a voltage generator for generating a program voltage or a pass voltage, which is applied to the word lines. The memory device also includes a page buffer group for applying program allow voltages or a program inhibit voltage to the bit lines and a control circuit for controlling the voltage generator and the page buffer group in response to a command. In a program operation of selected memory cells connected to a selected word line among the word lines, the control circuit controls the page buffer group such that the program allow voltages are increased stepwise according to a number of program loops performed on the selected memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.