Semiconductor chips having recessed regions
US12431442B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Jul 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/585
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip includes a semiconductor substrate including a device region, and an edge region surrounding the device region, a device layer on the semiconductor substrate, a wiring layer on the device layer, a side surface of the wiring layer at least partially defining a recessed region that is in the edge region such that the side surface of the wiring layer is exposed by the recessed region, and an upper insulating layer on the wiring layer. The recessed region extends from a side surface of the device layer toward the device region. A first portion of the upper insulating layer covers the side surface of the wiring layer that is exposed by the recessed region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.