Duty-cycle matched differential clock divider circuit
US12431907B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Jul 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a system and method of generating a duty-cycle matched differential clock divider circuit. The duty-cycle matched differential clock divider circuit may include a primary latch, differential latch, and a first inverter. The primary latch may be coupled to receive a feedback signal and complementary input clock signals. The primary latch may be configured to produce a first output signal. The differential latch may be coupled to receive the first output signal produced by the primary latch and the complementary input clock signals. The differential latch may be configured to produce a second output signal and a third output signal. The first inverter may be coupled to receive the second output signal produced by the differential latch, and may be configured to produce the feedback signal applied to an input of the primary latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.