Low latency block cipher in memory devices
US12432055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Dec 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0861
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A storage device includes multiple memory dies and a controller configured to: (i) encrypt a data block using a key schedule that includes a plurality of round keys generated from an encryption key, the encrypting resulting in an encrypted data block; (ii) during the encrypting, modify a key register during a first plurality of iterations, the key register being updated to a final state of the key register after a final iteration of the plurality of iterations; (iii) store the final state of the key register as a decryption key; and (iv) decrypt the encrypted data block using another key schedule that includes the plurality of round keys that are generated using the decryption key during a second plurality of iterations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.