Method and apparatus to mitigate word line staircase etch stop layer thickness variations in 3D NAND devices
US12432922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2020 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Jun 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus, a method and a system. The apparatus comprises a memory array including word lines defining a staircase structure, and a staircase etch stop layer including: a sandwich etch stop layer disposed on a top region the staircase and including a first etch stop layer and a third etch stop layer of a first material, and a second etch stop layer sandwiched between the first etch stop layer and the third etch stop layer and made of a second material having etch properties different from the first material; a precut etch stop layer disposed at a region of the staircase structure below the top region and including the second etch stop layer and the third etch stop layer and not the first etch stop layer; and contact structures extending through a dielectric layer and the staircase etch stop layer and landing on the word lines at the staircase structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.