Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology
US12432964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2020 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | May 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.