Structure having different gate dielectric widths in different regions of substrate
US12433014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Dec 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A structure and method of forming different high dielectric constant (high-K) gate dielectrics for different transistors on the same substrate, are disclosed. A first region includes a first transistor(s) on the substrate having a first gate structure having a first gate body over a first high-K gate dielectric. The first gate body and the first high-K gate dielectric have different widths defining a first width difference. A second region includes a second transistor(s) on the substrate having a second gate structure having a second gate body over a second high-K gate dielectric. The second gate body and the second high-K gate dielectric have different widths defining a second width difference. The first width difference is different than the second width difference, i.e., amongst transistors in the different regions. The different gate dielectric widths improve control of overlap capacitance of the transistors without increasing dopants or an annealing temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.