Space-charge-limited integrated circuit structure
US3936856A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 1974 |
| Grant date | Feb 3, 1976 |
| Priority date | — |
| Expiry date | May 28, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
A space-charge-limited integrated circuit structure featuring optimized geometry to allow maximum packing density of the transistors in a semiconductor substrate. The widths of any two isolated regions of the same conductivity type are established in relation to the width of the region separating the isolated regions. The width of the region which separates two isolated regions having the same conductivity type as the high resistivity substrate must be greater than 0.75 times the width of either of the isolated regions. Conversely, the width of the region which separates the isolated regions having the opposite conductivity type to the substrate must be greater than 0.25 times the width of either of the isolated regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.