High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
US3943542A · kind A · utility
26Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1974 |
| Grant date | Mar 9, 1976 |
| Priority date | — |
| Expiry date | Nov 6, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.