Jacob Riseman
34Patents
24h-index
24Co-inventors
81Inventor score
Filing activity: Sep 24, 1973 → Mar 21, 1986
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4944836A | Chem-mech polishing method for producing coplanar metal/insulator films on a substrate | Electricity | 382 | Expired |
| US4419809A | Fabrication process of sub-micrometer channel length MOSFETs | Emerging Cross-Sectional Technologies | 279 | Expired |
| US4234362A | Method for forming an insulator between layers of conductive material | Emerging Cross-Sectional Technologies | 236 | Expired |
| US4648937A | Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer | Emerging Cross-Sectional Technologies | 231 | Expired |
| US4671851A | Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique | Electricity | 158 | Expired |
| US4209349A | Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching | Emerging Cross-Sectional Technologies | 84 | Expired |
| US4419810A | Self-aligned field effect transistor process | Electricity | 73 | Expired |
| US4356211A | Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon | Electricity | 72 | Expired |
| US4521952A | Method of making integrated circuits using metal silicide contacts | Electricity | 63 | Expired |
| US4209350A | Method for forming diffusions having narrow dimensions utilizing reactive ion etching | Emerging Cross-Sectional Technologies | 61 | Expired |
| US4462040A | Single electrode U-MOSFET random access memory | Electricity | 56 | Expired |
| US4169000A | Method of forming an integrated circuit structure with fully-enclosed air isolation | Electricity | 55 | Expired |
| US4252579A | Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition | Emerging Cross-Sectional Technologies | 55 | Expired |
| US4090254A | Charge injector transistor memory | Electricity | 43 | Expired |
| US4729006A | Sidewall spacers for CMOS circuit stress relief/isolation and method for making | Electricity | 42 | Expired |
| US4546536A | Fabrication methods for high performance lateral bipolar transistors | Emerging Cross-Sectional Technologies | 38 | Expired |
| US4583106A | Fabrication methods for high performance lateral bipolar transistors | Electricity | 36 | Expired |
| US4506435A | Method for forming recessed isolated regions | Electricity | 34 | Expired |
| US4689113A | Process for forming planar chip-level wiring | Emerging Cross-Sectional Technologies | 34 | Expired |
| US4032058A | Beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads | Electricity | 31 | Expired |
| US4641170A | Self-aligned lateral bipolar transistors | Electricity | 31 | Expired |
| US4507171A | Method for contacting a narrow width PN junction region | Electricity | 27 | Expired |
| US3997963A | Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads | Electricity | 26 | Expired |
| US3943542A | High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same | Electricity | 26 | Expired |
| US4492717A | Method for forming a planarized integrated circuit | Electricity | 18 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.