Field effect transistor structure for minimizing parasitic inversion and process for fabricating
US3946419A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1974 |
| Grant date | Mar 23, 1976 |
| Priority date | — |
| Expiry date | Nov 7, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor with spaced source and drain regions of a first type conductivity in a monocrystalline semiconductor body having a background impurity of a second opposite type conductivity, the improvement being a buried layer of a second type conductivity impurity having an average concentration higher than the impurity concentration of the background impurity that is located just beneath the insulating layer in the field regions of the device and at a greater depth in the gate region, the depth in the gate region being approximately equal to the thickness of the field insulating layer less the thickness of the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.