Clock gated digital data encoding circuit
US3952298A · kind A · utility
11Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1975 |
| Grant date | Apr 20, 1976 |
| Priority date | — |
| Expiry date | Apr 17, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/245
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital data encoding circuit for use in a one-way transmission system utilizes three 8-bit multiplexers to generate and transmit a 64-bit message. Each bit in the message comprises a 4-chip, or time slot, code that includes an embedded clock therein. The encoding circuit repetitively generates the 64-bit coded message but only enables transmission of one message during periodically recurring intervals. In the event a priority message is sensed, the time between the intervals is reduced so that the rate of message transmission is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.