Logic network test system with simulator oriented fault test generator
US3961250A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 1974 |
| Grant date | Jun 1, 1976 |
| Priority date | — |
| Expiry date | May 8, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318371
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a technique for testing highly complex, functional logic where long sequences of test patterns are needed. A logic network to be tested comprises a large number of logic blocks. The inputs to several of these logic blocks are also the primary inputs (PI) to the logic network to be tested while the output of several of the logic blocks are also outputs (PO) of the logic network to be tested. However, the inputs and outputs of many logic blocks of the network to be tested are inaccessible since as is well known in large scale integration (LSI), a large number of internal circuit nodes cannot be probed directly. In accordance with the present disclosure, such a logic network to be tested is simulated and each of the logic blocks as well as the inputs and outputs of each of these logic blocks is uniquely defined. A first test pattern is then applied to the primary inputs (PI) of the network to set the logic levels on these primary inputs to known values. A particular one of the logic blocks within the network is then selected and a specific fault associated with the particular logic block is assumed. A test value for this assumed specific fault in the simulated network is …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.