Patent · US Expired

Testing embedded arrays

US3961252A · kind A · utility

52Cited by
3References
11Claims
0Family size

Assignee

Inventor

Key dates

Filing dateDec 20, 1974
Grant dateJun 1, 1976
Priority date—
Expiry dateDec 20, 1994

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C29/20
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, the address registers and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit to two or more positions of the register. The address and data registers are stepped through all of their states. The data register counter outputs may then be compared with the array outputs, thereby allowing one to check address selection as well as the ability to write or read at each of the storage locations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.