Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide
US3969749A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 1975 |
| Grant date | Jul 13, 1976 |
| Priority date | — |
| Expiry date | May 19, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30608
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process permitting control of the thickness of the thin layer of semiconductor material by first forming a slot of a predetermined depth in one surface so that the slot will be exposed during removal of material from the opposite surface should the thickness of the thin layer of semiconductor material become less than the depth of the slot, and a (110) oriented semiconductor substrate having a slot formed therein which is bounded by converging {111} planes. In a preferred embodiment the thickness control is realized by first preparing the slice of semiconductor material so that at least one of its surfaces has a (100) orientation. There is then formed on the surface of the slice having the (100) orientation an etch-resistant mask having a window opened therethrough such that the window defines on the surface of the slice two lines which are parallel to each other and to lines defined by the intersection of {111} planes with the surface of the slice. Semiconductor material is then removed through the windows by etching to produce a slot having a depth greater than thickness to which the single crystal semiconductor material is to be subsequently processed. A vapor deposited support …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.