Diffusion control for controlling parasitic capacitor effects in single FET structure arrays
US3975220A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1975 |
| Grant date | Aug 17, 1976 |
| Priority date | — |
| Expiry date | Sep 5, 1995 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method in the manufacture of FET single device memory cells and arrays for controlling a doped oxide diffusion profile and thereby controlling substrate diffusion and doped oxide diffusion source overlap and controlling the inherent formation of parasitic capacitance. This is accomplished by controlling the variation of four interrelated essential parameters in the production of a single device memory cell array with the consequent result of minimizing said parasitic capacitance encountered in certain overlap conditions and thereby maintaining and increasing device performance. Process conditions which are controlled relative to one another are the thickness of the doped oxide on a monocrystalline semiconductor silicon substrate, the amount of over etch carried out in the formation of a diffusion source island, the thickness of oxide formed on unprotected substrate areas during diffusion drive-in, and the depth of a particular diffusion into the substrate, known as X.sub.j.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.