One-bit full adder
US3978329A · kind A · utility
7Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1975 |
| Grant date | Aug 31, 1976 |
| Priority date | — |
| Expiry date | Sep 12, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed, low-power 1-bit adder includes a combination of current-mode switches connected in a dual tree configuration in series with respective constant current sources and summing resistors. Input operand signals select particular tree paths, thereby controlling the voltage appearing across the summing resistors and sum and carry output drivers responsive to these voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.