Clocked IGFET voltage level sustaining circuit
US3986044A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1975 |
| Grant date | Oct 12, 1976 |
| Priority date | — |
| Expiry date | Sep 12, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level sustaining circuit for an IGFET driver circuit having an output node includes a first IGFET coupled between a voltage supply conductor and an output node of a driver circuit. The gate of the first IGFET is coupled to a source of a second IGFET having its gate and drain connected to the voltage supply conductor. A boosting capacitor is connected between the gate of the first IGFET and a conductor to which a refresh pulse is applied. The refresh pulse need be applied only often enough and be of sufficient magnitude to turn on the first IGFET sufficiently hard that the output node is held at the voltage of the voltage supply conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.