High performance latch circuit
US3986057A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1975 |
| Grant date | Oct 12, 1976 |
| Priority date | — |
| Expiry date | Jun 30, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/287
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a high performance logically hazard-free latch circuit compatible with TTL technology. The occurrence of both a clock and data signal provides an inverted data output signal at the output node which is fed back to the base electrode of a multi-emitter transistor. The output node then remains latched at the desired logic level until the occurrence of a subsequent clock signal. Also disclosed are techniques for improving the capabilities of the latch and for accepting additional clock and data inputs. The polarity-hold latch circuit disclosed herein is advantageously implemented in semiconductor integrated circuit technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.