Content addressable memory system employing charge coupled device storage and directory registers and N/(1-H) counter refresh synchronization
US3997882A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 1975 |
| Grant date | Dec 14, 1976 |
| Priority date | — |
| Expiry date | Apr 1, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory system for accessing blocks of data stored in circular charge coupled shift registers in response to a tag word presented to a directory unit comprising circular charge coupled shift registers. The memory includes clocking and logic circuitry for providing selective, high speed clocking of blocks and directory unit registers for both read and write operations. Additional logic facilitates masked directory searches at selective clock rates. Automatic synchronization of fast and slow clocked registers is provided by a counter of predetermined count corresponding to the formula N/(1-H) where H is the number of bits per circular register and H equals the ratio of slow to fast shift rates. A use bit register in the directory unit and a bookkeeping loop register in each module further aid in synchronization of the memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.