High density semiconductor chip organization
US4006492A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1975 |
| Grant date | Feb 1, 1977 |
| Priority date | — |
| Expiry date | Jun 23, 1995 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip layout including a plurality of logic cells arranged in columns. A cell may encompass one of two different magnitudes of area in the chip; and each column contains only cells having the same area. The layout is particularly appropriate for level sensitive logic systems which utilize both combinatorial as well as sequential networks. The combinatorial (combinational) networks are less orderly and require a greater number of selectable input connections, hence more area, than the sequential circuits. The wide and narrow columnar architecture allows a much greater circuit packing density on a chip, resulting in a substantial increase in the number of circuits for a given chip area. Performance is also increased because of the reduced area required by the sequential circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.