Overlay metallization field effect transistor
US4016643A · kind A · utility
16Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1976 |
| Grant date | Apr 12, 1977 |
| Priority date | — |
| Expiry date | Apr 12, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-frequency, high-power FET constructed upon a planar substrate with a repeated pattern of gate, source, and drain connections wherein any two are connected with metallization layers adjacent to and separated from the semiconductor substrate. The third element is interconnected with an overlay metallization layer separated from the lower two metallization layers by an insulating dielectric. The overlay layer is preferably grounded for minimum feedback capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.