Method for forming integrated circuit regions defined by recessed dielectric isolation
US4044454A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1975 |
| Grant date | Aug 30, 1977 |
| Priority date | — |
| Expiry date | Apr 16, 1995 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a silicon substrate comprising initially introducing conductivity-determining impurities into the substrate to form at least one region of one-type conductivity at the surface of said substrate. Then, a mask comprising a composite of a bottom layer of silicon dioxide and a top layer of silicon nitride is formed over at least a portion of the surface of said introduced regions. The substrate is then subsequently thermally oxidized to an extent sufficient to form regions of recessed silicon dioxide abutting and thus laterally defining said region of one-type conductivity. In this manner, it is ensured that the recessed silicon dioxide will abut introduced region irrespective of the extent of the "bird's beak" normally associated with thermal oxidation utilizing silicon dioxide-silicon nitride masking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.