Process for fabricating small geometry semiconductive devices including integrated components
US4049944A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1975 |
| Grant date | Sep 20, 1977 |
| Priority date | — |
| Expiry date | Aug 20, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2654
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a process for fabricating small geometry electronic devices, including a variety of integrated optical devices. The process includes the steps of holographically exposing a resist masking layer to a plurality of optical interference patterns in order to develop a masking pattern on the surface of a semiconductive body. Thereafter, regions of the body exposed by openings in the masking pattern are ion beam machined to thereby establish very small dimension undulations in these regions. These closely spaced undulations have a variety of uses in optical devices as will be described. The present invention is not limited to the geometry control of semiconductive structures, and may also be used in the geometry control of metallization patterns which have a variety of applications, or the geometry control of any ion beam sensitive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.