Conditional bypass of error correction for dual memory access time selection
US4058851A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 1976 |
| Grant date | Nov 15, 1977 |
| Priority date | — |
| Expiry date | Oct 18, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and an apparatus for conditionally bypassing the error correction function of a large scale integrated (LSI) semiconductor random access memory (RAM) is disclosed. A content addressable memory (CAM) is utilized to store the addresses of the addressable locations in the RAM in which an error was previously detected, and on each memory reference both the CAM and the RAM are simultaneously referenced by the same address. Upon a memory reference, the read data from, i.e., the date read out of, the RAM is concurrently coupled directly to an Interface Register and directly to the error detection and correction circuitry (ECC) and thence to the Interface Register. If the CAM does not contain the address, the read data that is coupled to the Interface Register is gated out at a first relatively early gate pulse. However, if the CAM does contain the address, the corrected read data from the ECC is then gated out of the Interface Register at a second relatively later gate pulse. Thus, when no error exists in the read data, the RAM is accessed at a relatively fast access time while, if an error exists in the read data, the RAM is accessed at a relatively slower access time to prov…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.