James H. Scheuneman
26Patents
17h-index
15Co-inventors
74Inventor score
Filing activity: Sep 20, 1976 → Mar 19, 1990
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4112502A | Conditional bypass of error correction for dual memory access time selection | Physics | 174 | Expired |
| US4633434A | High performance storage unit | Physics | 108 | Expired |
| US4058851A | Conditional bypass of error correction for dual memory access time selection | Physics | 100 | Expired |
| US4600986A | Pipelined split stack with high performance interleaved decode | Physics | 94 | Expired |
| US5060145A | Memory access system for pipelined data paths to and from storage | Physics | 61 | Expired |
| US4531213A | Memory through checking system with comparison of data word parity before and after ECC processing | Physics | 45 | Expired |
| US4996688A | Fault capture/fault injection system | Physics | 40 | Expired |
| US4757440A | Pipelined data stack with access through-checking | Physics | 39 | Expired |
| US4652993A | Multiple output port memory storage module | Physics | 38 | Expired |
| US4139148A | Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory | Physics | 33 | Expired |
| US4070706A | Parallel requestor priority determination and requestor address matching in a cache memory system | Physics | 27 | Expired |
| US4926426A | Error correction check during write cycles | Physics | 25 | Expired |
| US4092713A | Post-write address word correction in cache memory system | Physics | 25 | Expired |
| US4649475A | Multiple port memory with port decode error detector | Physics | 22 | Expired |
| US4163147A | Double bit error correction using double bit complementing | Physics | 21 | Expired |
| US4697233A | Partial duplication of pipelined stack with data integrity checking | Physics | 21 | Expired |
| US4953131A | Unconditional clock and automatic refresh logic | Physics | 20 | Expired |
| US4357686A | Hidden memory refresh | Physics | 17 | Expired |
| US4918695A | Failure detection for partial write operations for memories | Physics | 17 | Expired |
| US4292674A | One word buffer memory system | Physics | 14 | Expired |
| US4962501A | Bus data transmission verification system | Physics | 14 | Expired |
| US4918696A | Bank initiate error detection | Physics | 10 | Expired |
| US5068782A | Accessing control with predetermined priority based on a feedback arrangement | Physics | 10 | Expired |
| US4727510A | System for addressing a multibank memory system | Physics | 9 | Expired |
| US4989210A | Pipelined address check bit stack controller | Physics | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.