Clock generation network for level sensitive logic system
US4063078A · kind A · utility
14Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1976 |
| Grant date | Dec 13, 1977 |
| Priority date | — |
| Expiry date | Jun 30, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved clock generation network. The improved clock generation network is particularly adapted to, and has particular utility when employed in a Level Sensitive Logic System generally of the type disclosed in U.S. Pat. No. 3,783,254, of common assignee. The disclosed clock generation network also has particular utility in a Level Sensitive Embedded Array Logic System of the type disclosed in U.S. patent application Ser. No. 701,052, filed June 30, 1976, by Messrs. E. B. Eichelberger, E. I. Muehldorf, R. G. Walther and T. W. Williams and of common assignee.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.