Method for forming a narrow channel length MOS field effect transistor
US4078947A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1976 |
| Grant date | Mar 14, 1978 |
| Priority date | — |
| Expiry date | Aug 5, 1996 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/919
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.