Epitaxial process for the fabrication of a field effect transistor having improved threshold stability
US4089712A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1977 |
| Grant date | May 16, 1978 |
| Priority date | — |
| Expiry date | May 17, 1997 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/167
Abstract
An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer. In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact. In an alternate embodiment of the method for forming a field effect transistor, a first ion implantation is formed in the drain region, such that the peak impurity concentration is located well within the body spaced from the surface…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.