Method for adjusting the leakage current of silicon-on-sapphire insulated gate field effect transistors
US4091527A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1977 |
| Grant date | May 30, 1978 |
| Priority date | — |
| Expiry date | Mar 7, 1997 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/91
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for adjusting the leakage current of insulated gate field effect transistors comprised of silicon mesas epitaxially formed on a sapphire substrate, wherein the leakage current of a P channel transistor is increased by preoxidizing the silicon prior to standard processing and/or wherein the leakage current is decreased by annealing the silicon in a reducing atmosphere in addition to standard processing steps. The leakage current of an N channel transistor is reduced by preoxidizing the silicon of the transistor prior to forming the transistor and/or is increased by annealing in a reducing atmosphere in addition to the steps necessary for forming the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.