Post-write address word correction in cache memory system
US4092713A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 1977 |
| Grant date | May 30, 1978 |
| Priority date | — |
| Expiry date | Jun 13, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for and a method of providing error correction of the address word of a cache memory system (CMS) utilizing post-write storage of the least recently used (LRU) block of data words. Error correction circuitry (ECC) is provided at the output of the address buffer (CAB) portion of the cache memory system so that the address word that specifies the addressable location in the main storage unit (MSU) into which the block of data words, which block of data words is stored in the data buffer (CDB) portion of the cache memory, is to be stored or written-back is error corrected upon readout. This error correction of the address word ensures that correctable errors in the address buffer provided address words do not generate a Miss signal by the storage interface unit (SIU) which, in turn, requires a MSU reference even though the desired address word and the associated data word are available in the cache memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.