MOS Buffer circuit
US4103189A · kind A · utility
17Cited by
11References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1977 |
| Grant date | Jul 25, 1978 |
| Priority date | — |
| Expiry date | Jul 25, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An MOS buffer circuit which may be employed as part of a electrically programmable read-only memory or other MOS integrated circuit is described. The buffer may be "powered down" when the memory is in a standby mode. Low threshold (zero threshold) voltage devices are employed in the circuit along with depletion mode transistors and enhancement mode transistors in a manner which permits the buffer to be readily powered down.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.