Technique for preventing forward biased epi-isolation degradation
US4113512A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1976 |
| Grant date | Sep 12, 1978 |
| Priority date | — |
| Expiry date | Oct 28, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Certain types of silicon integrated circuits are embodied as having diffused isolation regions surrounding epitaxial regions. Although normally operated in a reverse bias mode, such regions may become forward biased when sourcing current for certain circuit applications. Certain types of ionized impurities lodged in the isolation region can then migrate into the depletion region and the epitaxial region of the device during a forward bias condition. Such contaminants can be expected to produce generation-recombination centers in the depletion layer of the device which, when the isolation region is then reverse biased, will produce significant increases in junction leakage current. The magnitude of this reverse bias leakage current will depend upon both the contaminant concentration and the width of the depletion region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.