Semiconductor integrated circuit isolated through dielectric material and a method for manufacturing the same
US4131909A · kind A · utility
20Cited by
9References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1976 |
| Grant date | Dec 26, 1978 |
| Priority date | — |
| Expiry date | Oct 26, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6758
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit includes first and second island regions, surrounded by a bottomed dishlike dielectric layer formed on one side of a support body. A MOS transistor element is formed in the first island region, whose gate region is located at the bottom side of the island region. The gate electrode is connected to a bottom portion of the second island region, which is used as a gate electrode contact region, in the support body using a interconnection lead. There is a method for manufacturing the above device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.