Method of fabricating conductive buried regions in integrated circuits and the resulting structures
US4149177A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 1976 |
| Grant date | Apr 10, 1979 |
| Priority date | — |
| Expiry date | Sep 3, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76216
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an oxide isolated semiconductor structure having an epitaxial layer formed on a monocrystalline substrate, a buried, laterally extending, PN junction in said structure, and oxidized isolation regions extending through said epitaxial layer to said PN junction, thereby to form a plurality of electrically isolated pockets of semiconductor material, a dopant is located in those regions of the semiconductor material directly adjacent the oxidized isolation regions. This dopant is often referred to as the field predeposition. The processes which result in the subsequent formation of insulating material to create isolated epitaxial pockets also result in the formation of a conductive buried region resulting from that portion of the field predeposition between the epitaxial pockets and portions of the wall of the insulating material. If desired, a collector sink then may be formed in the epitaxial pocket without disrupting the function of the conductive buried region. Among other embodiments, the conductive buried region may function as a collector sink bypass to allow manufacture of smaller memory circuits than those heretofore available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.