Martin Alter
32Patents
11h-index
20Co-inventors
75Inventor score
Filing activity: Sep 3, 1976 → Jul 30, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7315052B2 | Power FET with embedded body pickup | Electricity | 162 | Expired |
| US5447876A | Method of making a diamond shaped gate mesh for cellular MOS transistor array | Electricity | 107 | Expired |
| US5517046A | High voltage lateral DMOS device with enhanced drift region | Electricity | 71 | Expired |
| US5355008A | Diamond shaped gate mesh for cellular MOS transistor array | Electricity | 71 | Expired |
| US4914546A | Stacked multi-polysilicon layer capacitor | Electricity | 58 | Expired |
| US5439764A | Mask having multiple patterns | Physics | 28 | Expired |
| US4979001A | Hidden zener diode structure in configurable integrated circuit | Electricity | 23 | Expired |
| US7145211B2 | Seal ring for mixed circuitry semiconductor devices | Electricity | 16 | Expired |
| US5034346A | Method for forming shorting contact for semiconductor which allows for relaxed alignment tolerance | Emerging Cross-Sectional Technologies | 16 | Expired |
| US7087973B2 | Ballast resistors for transistor devices | Electricity | 13 | Expired |
| US6621138B1 | Zener-like trim device in polysilicon | Electricity | 11 | Expired |
| US7195952B2 | Schottky diode device with aluminum pickup of backside cathode | Electricity | 11 | Expired |
| US5045966A | Method for forming capacitor using FET process and structure formed by same | Electricity | 11 | Expired |
| US4951101A | Diamond shorting contact for semiconductors | Emerging Cross-Sectional Technologies | 10 | Expired |
| US7501693B2 | LDO regulator with ground connection through package bottom | Electricity | 9 | Active |
| US6900538B2 | Integrating chip scale packaging metallization into integrated circuit die structures | Electricity | 8 | Expired |
| US6395591B1 | Selective substrate implant process for decoupling analog and digital grounds | Electricity | 8 | Expired |
| US5254486A | Method for forming PNP and NPN bipolar transistors in the same substrate | Electricity | 8 | Expired |
| US5439841A | High value gate leakage resistor | Electricity | 7 | Expired |
| US6917105B2 | Integrating chip scale packaging metallization into integrated circuit die structures | Electricity | 7 | Expired |
| US4149177A | Method of fabricating conductive buried regions in integrated circuits and the resulting structures | Electricity | 7 | Expired |
| US5589702A | High value gate leakage resistor | Electricity | 6 | Expired |
| US7843019B2 | Seal ring for mixed circuitry semiconductor devices | Electricity | 3 | Active |
| US7211893B2 | Integrating chip scale packaging metallization into integrated circuit die structures | Electricity | 3 | Expired |
| US8525257B2 | LDMOS transistor with asymmetric spacer as gate | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.